High-speed interface circuits utilize clock signals to control the timing of data transmission and reception. High data rate communication is often facilitated using complimentary clock signals. Complimentary clock signals allow data to be transmitted and received on rising and falling clock edges. Complimentary clock signals, however, that are generated and/or provided by existing clock distribution circuits may be subject to skew and/or duty-cycle variations. Clock generation and/or distribution circuits also may occupy a large area on the integrated circuit and consume significant amounts of power.
Like reference numerals refer to corresponding parts throughout the drawings.